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Parallel Fault Simulation in Large-Scale Integration Logic Networks

IP.com Disclosure Number: IPCOM000099707D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Iyengar, V: AUTHOR [+2]

Abstract

A technique is described whereby simulation of faults in logic networks, as used in very large-scale integrated (VLSI) circuitry, is performed in parallel, so as to be applicable to existing hardware simulation engines and to software simulators with similar characteristics. A new concept of independence between faults characterizes the faults that can be simulated in parallel. This concept is used to improve the efficiency of fault simulation over existing techniques.

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This is the abbreviated version, containing approximately 52% of the total text.

Parallel Fault Simulation in Large-Scale Integration Logic Networks

       A technique is described whereby simulation of faults in
logic networks, as used in very large-scale integrated (VLSI)
circuitry, is performed in parallel, so as to be applicable to
existing hardware simulation engines and to software simulators with
similar characteristics.  A new concept of independence between
faults characterizes the faults that can be simulated in parallel.
This concept is used to improve the efficiency of fault simulation
over existing techniques.

      In prior art, simulation engines typically simulated a logic
network with one injected fault to determine the response of the
faulted machine.  During the fault simulation operation, for example,
using pseudo-random input patterns, much of the simulation time was
spent simulating the random pattern resistant faults.  To simulate
the fault machine response to an input pattern for a random pattern
resistant fault, only a small portion of the logic network requires
simulation.  This could be used in an event-driven approach to speed
up the simulation.  Attempting to perform the event driven form of
simulation is difficult in pipelined hardware simulation engines,
where the order of evaluation is determined when the model is
compiled.  The concept described herein attempts to implement
efficient algorithms for these hardware engines, as an improvement
over the prior art.

      A realistic environment is considered where certain structured
design rules are followed.  It is assumed that scan design techniques
are used to reduce the problem of test generation of sequential
designs to test generation of combinational logic.  It is also
assumed that the test protocol is such that the fault simulation
performed on an equivalent combinational logic model.

      Faults associated with logic gates either reside at the input
or output pins of a logic gate, and are referred to as "stuck-at"
faults.  The fault site refers to the location where the fault is
residing in the model.  Faults that add interconnections between
logic gates, such as bridging faults between signals, are not
considered.

      In the formulation of the algorithm, consideration has been
given to accomplish more during the simulation.  One way is to inject
more than one fault simultaneously in the simulation model.

      The terminology used is defined as follows:  Up-cone of some
input or output pin, p, of a gate in the combinational network is the
portion of network obtained by traversing all paths to p from the
PIs.  The PIs...