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# Parity Predict for Sequencer Invalid State Transitions

IP.com Disclosure Number: IPCOM000099719D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 61K

IBM

## Related People

Andraschko, MR: AUTHOR

## Abstract

Described is a method to predict even parity for invalid state transitions, which are valid sequencer states, to detect these state changes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Parity Predict for Sequencer Invalid State Transitions

Described is a method to predict even parity for invalid
state transitions, which are valid sequencer states, to detect these
state changes.

All sequencers have states, and normally they have invalid
states.  Invalid states are states that logically cannot happen.
Valid state transitions are when the sequencer changes from one valid
state to another valid state.  Invalid state transitions are also
state changes from one valid state to another valid state; however,
the "transition" from one state to another specific state is not
possible by design.  Therefore, invalid state transitions are
possible when the hardware fails and may go undetected, destroying
vital data and causing data integrity problems.

A solution to this problem is to predict parity based on the
current state of the machine and the expected next state transition.
ODD parity (the total number of data and parity bits set to a binary
"one" is odd) is predicted for all the valid state transitions and
EVEN parity (the total number of data and parity bits set to a binary
"one" is even) is predicted for all the invalid state transitions.

The figure shows parity predicted for the state machine shift
register latches (SRLs) currently in state "000". There are eight
possible states for this sequencer of which five states are valid.
The valid states are 000, 010, 011, 100, and 110.  There are three
invalid states --...