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Browse Prior Art Database

New Substrate Contact Fabrication Techniques

IP.com Disclosure Number: IPCOM000099720D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Nastasi, V: AUTHOR [+3]

Abstract

Semiconductor structures employing polysilicon trench isolation exhibit isolation leakage paths due to defects in trench sidewall insulation. A sidewall RIE (reactive ion etch) step used to form the sidewall, and to open the bottom of the trench for substrate contact, is identified as a primary cause of these insulation defects. They may be eliminated by the use of the technique here disclosed by which substrate contacts may be obtained without opening the bottom of the trench.

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This is the abbreviated version, containing approximately 100% of the total text.

New Substrate Contact Fabrication Techniques

       Semiconductor structures employing polysilicon trench
isolation exhibit isolation leakage paths due to defects in trench
sidewall insulation.  A sidewall RIE (reactive ion etch) step used to
form the sidewall, and to open the bottom of the trench for substrate
contact, is identified as a primary cause of these insulation
defects.  They may be eliminated by the use of the technique here
disclosed by which substrate contacts may be obtained without opening
the bottom of the trench.

      The disclosed contact fabrication technique employs an extra
masking step to wet etch the Si02 sidewall, followed by a polysilicon
deposition to obtain the substrate contact. Fig. 1 shows the
structure resulting after standard processing through isolation,
etc., and the use of a substrate contact mask (photoresist) 1 to
block out all but the eventual contacts.  The oxide sidewall 2 and
polysilicon-filled trench 3 are seen to be in place.  A wet, or
selective dry etch, is next used to remove the sidewall Si02 2 in the
open areas, leaving the structure shown in Fig. 2.  Standard
processing is then continued, including polysilicon metallization, to
obtain the structure shown in Fig. 3, in which the desired
polysilicon substrate contact 4 is obtained via the trench.  This
approach avoids the need for sidewall removal by RIE and the
potential for exposure to sidewall insulation defects and yield loss.