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Multi-Phase Analog-To-Digital Converter

IP.com Disclosure Number: IPCOM000099729D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Coker, JD: AUTHOR [+3]

Abstract

Described is a circuit for implementing a multi-phase analog-to-digital "flash" converter which makes multiple conversions during each logic cycle. Analog-to-digital converters (ADCs) are used to quantize an analog signal into a logical representation. ADCs which sample analog signals at high speeds are generally constructed using a comparator network and are commonly referred to as "flash" converters.

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This is the abbreviated version, containing approximately 52% of the total text.

Multi-Phase Analog-To-Digital Converter

       Described is a circuit for implementing a multi-phase
analog-to-digital "flash" converter which makes multiple conversions
during each logic cycle.  Analog-to-digital converters (ADCs) are
used to quantize an analog signal into a logical representation.
ADCs which sample analog signals at high speeds are generally
constructed using a comparator network and are commonly referred to
as "flash" converters.

      A multi-phase flash ADC is a hardware structure which allows
relaxed circuit speed requirements for a reasonable circuit real
estate increase.  This structure relieves the speed requirements of
the ADC and following logic circuits by a factor of two or more.  The
presented ADC type is increased to a four-phase or greater design
through straightforward means.

      Fig. 1 illustrates a conventional flash ADC structure. This
design comprises a comparator array, a latch array that holds the
result from the comparator array, combinational decode logic, and a
final set of latches that hold the ADC conversion result.  The
comparator array is used to relate the incoming analog signal to a
set of incremental reference voltage levels (derived from a resistor
ladder).  The result from the comparator array is latched and thus
forms a quantized representation of the analog signal at some
instance in time.  Decode combinational logic is then utilized to
compress the comparator result into a binary-weighted representation.
 Fig. 2 is an example of the decode combinational logic function for
a 6-...