Browse Prior Art Database

Trench Transistor

IP.com Disclosure Number: IPCOM000099732D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Phillips, A: AUTHOR [+2]

Abstract

A symmetric bipolar transistor, having a controllable level of boron out-diffusion from the polysilicon base and reduced processing complexity, can be fabricated by replacing the sidewall masked isolation with a medium depth trench.

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Trench Transistor

       A symmetric bipolar transistor, having a controllable
level of boron out-diffusion from the polysilicon base and reduced
processing complexity, can be fabricated by replacing the sidewall
masked isolation with a medium depth trench.

      Conventional processing is used to process the wafer to the
point of the trench isolation being formed in the wafer.  Next, a
blanket oxide layer is grown over the epi-layer, which is then
followed by a layer of nitride.  Then, a medium depth trench is
reactive ion etched through the blanket layer of dielectrics, which
layer stops above the out-diffused subcollector (S/C).  A layer of
oxide and/or dielectric is then deposited along the trench base and
walls.

      Now, the trench is filled with in-situ doped P+ polysilicon.
The doped polysilicon is then etched and/or polished flush with the
nitride to form the structure of Fig. 1.

      The doped polysilicon is then selectively etched away to form a
shallow trench, and the sidewall oxide is removed by a wet etch to
form the structure of Fig. 2 with undercut regions A and B.

      In succession:  a) a layer of intrinsic polysilicon is
deposited, followed by  b) a layer of in-situ doped P+ polysilicon,
which is followed by  c) a layer of TaSi2, which structure is then
planarized as seen in Fig. 3.

      The stack is then re-oxidized adjacent to the pedestal. The
amount of oxidation is sufficient to re-oxidize all of the
polysilicon...