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Differential BICMOS Receiver With Feedback

IP.com Disclosure Number: IPCOM000099735D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Buchholtz, TC: AUTHOR [+3]

Abstract

Described is a differential BiCMOS clock receiver for BiCMOS VLSI logic chips. As a processor gets faster, noise generated on a card also increases. Consequently, it is imperative to have a system master clock that is low in generating noise and also high in noise rejection. To improve system cycle time, it is necessary to have a good system clock distribution. The system performance is limited by logic delay and clock distribution delay. The clock distribution delay is the combination of clock delay and all card and chip clock skews. The differential BiCMOS clock receiver addresses this problem.

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Differential BICMOS Receiver With Feedback

       Described is a differential BiCMOS clock receiver for
BiCMOS VLSI logic chips.  As a processor gets faster, noise generated
on a card also increases.  Consequently, it is imperative to have a
system master clock that is low in generating noise and also high in
noise rejection.  To improve system cycle time, it is necessary to
have a good system clock distribution.  The system performance is
limited by logic delay and clock distribution delay.  The clock
distribution delay is the combination of clock delay and all card and
chip clock skews.  The differential BiCMOS clock receiver addresses
this problem.

      This BiCMOS circuit is designed to operate with a differential
input voltage swing from 0.00V to -0.5V (see the figure).  A receiver
converts this low-voltage swing to BiCMOS voltage levels of 0.0V to
2.8V to drive BiCMOS logic circuits.  If IN1 is at 0V and IN2 is at
-0.5V, then Q1 turns on and Q2 turns off. Node 'A' is pulled down to
0V, turning off T1 and Q5.  Node 'B' is pulled up to VDD, turning on
T4 and Q3.  This causes nodes 'OUT1' and 'OUT2' to switch from 0V to
2.8V and from 2.8V to 0V, respectively.  If IN1 is at -0.5V and IN2
is at 0V, then nodes 'OUT1' and 'OUT2' switch in the reverse order.
T3 and T6 are used to pull nodes 'OUT1' and 'OUT2' to ground.  Vs is
fed back to the clock module, which produces the differential inputs.
 By knowing the condition of the inputs, Vs may be adjuste...