Browse Prior Art Database

High-Speed Programmable Servo Pattern Generator for Disk Drives

IP.com Disclosure Number: IPCOM000099739D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Brown, DH: AUTHOR [+2]

Abstract

The figure illustrates a device used to generate complex digital waveforms used for writing servo patterns on disk drives or any other purpose where sequences of data are needed. This device shifts the data out serially, 1 bit wide synchronized to the pattern generator clock. The pattern generator described is completely programmable. It includes a sequencer to fetch and execute instructions, a shift register to shift out the bit serial stream, and a memory to hold instructions and data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Speed Programmable Servo Pattern Generator for Disk Drives

       The figure illustrates a device used to generate complex
digital waveforms used for writing servo patterns on disk drives or
any other purpose where sequences of data are needed.  This device
shifts the data out serially, 1 bit wide synchronized to the pattern
generator clock.  The pattern generator described is completely
programmable.  It includes a sequencer to fetch and execute
instructions, a shift register to shift out the bit serial stream,
and a memory to hold instructions and data.

      The figure shows a block diagram of the pattern generator's
major components.  Instructions and data are stored in memory.  For
each instruction executed, a block of data bits between 9 and 16 bits
long is shifted with the execution of the instruction.  The memory is
32 bits wide. However, 16 bits of each location contain the
instruction, and 16 bits contain the block of data associated with
the corresponding instruction.  The instructions essentially are used
only to calculate the address of the next instruction and to tag the
number of bits of data to shift out before fetching the next
instruction. The storage address register (SAR) is used to address
the next instruction when the current instruction completes. Because
the instructions cannot perform arithmetic or comparisons, the logic
is very simple, and operation proceeds quickly without interruptions
in the data stream.

      There are eight instructions:
      ASSIGN    Increment the SAR after this instruction completes. 1
HOLD      Execute this instruction N times before incrementing the
SAR.
      BRANCH    Replace the SAR with the addr...