Browse Prior Art Database

Electrical Measurement of Gate Level Overlay

IP.com Disclosure Number: IPCOM000099741D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Sheets, JE: AUTHOR

Abstract

A device allows quick, efficient electrical measurement of a misalignment between a gate level (typically, polysilicon) and a recessed oxide (ROX) level.

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Electrical Measurement of Gate Level Overlay

       A device allows quick, efficient electrical measurement
of a misalignment between a gate level (typically, polysilicon) and a
recessed oxide (ROX) level.

      The figure depicts the device.  A square, thin oxide region is
defined using standard recessed oxide isolation processing.  After
gate oxidation, the gate level (polysilicon) is patterned to form the
desired '+' sign. These two images form four discrete field effect
transistors (FETs) which are labeled  1, 2, 3 and 4.  Notice that the
four FETs are designed to have identical lengths and widths.

      Five electrical pads (typically, aluminum) are required for the
overlay measurements.  Large, easily measured saturated drain
currents for each of the four FETs are measured in the following
manner:
   Apply V-high (typically, 3.5 or 5V) to a gate pad e and 1 of 4
device drains (a,b,c, or d), and measure the resultant current on an
adjacent drain with the grounded ammeter. 1

      EXAMPLE:  Device 1 drain current is found by applying V-high to
pads a and e, grounding b, and measuring the current.

      The actual overlay determination is a matter of comparing the
magnitude of the currents on the four devices. Notice that with
perfect alignment between the ROX and gate levels, the four-device
currents are identical given their identical width-to-length ratios.
However, if the gate is misaligned relative to the recessed oxide,
the device w...