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Browse Prior Art Database

CPU/FPU Peer-To-Peer Interface

IP.com Disclosure Number: IPCOM000099748D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Beacom, TJ: AUTHOR [+4]

Abstract

The figure illustrates a peer-to-peer (P/P)-type interface between a central processing unit (CPU) chip and a floating-point unit (FPU) coprocessor chip for a complex instruction set computer (CISC) with two levels of instructions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

CPU/FPU Peer-To-Peer Interface

       The figure illustrates a peer-to-peer (P/P)-type
interface between a central processing unit (CPU) chip and a
floating-point unit (FPU) coprocessor chip for a complex instruction
set computer (CISC) with two levels of instructions.

      The processor in question is a CISC that boasts instructions
that usually are not executed in one machine cycle.  A typical
instruction, FP ADD, involves fetching the first operand from
storage, fetching the second operand from storage, adding the two
operands, and then storing the result back to storage.  For this
processor, the instructions (HIGH LEVEL (HL) instructions), such as
FP ADD are fetched from main store by the CPU.  An HL instruction,
however, is not directly executed by the hardware, but calls a
microroutine of other LOW LEVEL (LL) instructions which the hardware
actually executes.  For the HL instruction FP ADD, there is an LL
instruction for the fetch of the first operand, an LL instruction for
the fetch of the second operand, an LL instruction for the raw
addition, and an LL instruction for storing the result.  A series of
LL instructions interprets an HL instruction for the hardware.  Thus,
LL instructions break down an HL instruction into separate operations
for the hardware to execute.

      Since there are two levels of instructions (HL, LL), and since
HL instructions are interpreted such that LL instructions control FPU
operations, the CPU and FPU are tied toge...