Browse Prior Art Database

Pageable Expansion Ram for Independent Command Lists

IP.com Disclosure Number: IPCOM000099779D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Lochner, DL: AUTHOR [+2]

Abstract

Disclosed is a circuit card which adds memory to a PC, PC-XT, or PC-AT, above the normal 640K DOS region, for use in a multi-station test system to store separate, and possibly different, "command lists" for each station. The card provides 384 Kbytes (64 K per Station), with the design extendable to larger amounts or to more stations. Paging circuits allow selectable portions of this RAM to share an unused segment of the PC's address space.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Pageable Expansion Ram for Independent Command Lists

       Disclosed is a circuit card which adds memory to a PC,
PC-XT, or PC-AT, above the normal 640K DOS region, for use in a
multi-station test system to store separate, and possibly different,
"command lists" for each station.  The card provides 384 Kbytes (64 K
per Station), with the design extendable to larger amounts or to more
stations.  Paging circuits allow selectable portions of this RAM to
share an unused segment of the PC's address space.

      In the card block diagram of the figure, address, data, and
control signals are redriven by Buffer 1 so that the card places the
least load on the PC Bus.  RAM 2 is shown divided into six equal
portions.  When enabled, one RAM portion at a time can be gated into
the PC's address space.

      RAM selection is controlled by system software, which places a
control value into Register 3 to specify access to one of the six
portions of the RAM.  The register value is decoded by RAM Select
Logic 4 to activate the specified RAM.

      Card ID Port 5 is read by system software to determine whether
the card is present and/or to verify its revision level.  Address
Decode circuit 6 monitors the PC address bus to allow read or write
operations, as appropriate, to/from Register 3 or Card ID Port 5.

      The card is used in a test system by a PC software program
known as a command list supervisor.  When the supervisor is loaded
into PC memory and begins...