Browse Prior Art Database

Invalid Register Access Protection

IP.com Disclosure Number: IPCOM000099792D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Clark, SD: AUTHOR [+2]

Abstract

Described is a method that prevents a processor from reading or writing registers in logic while the logic is per- forming a triggered function. Some functions of computer system logic are triggered by setting bits in registers. Some functions do not stop the processor that sets the bits. Because the processor is not stopped, there is no protection other than software convention against the processor reading or writing registers that the logic is using and changing. This might result in the processor reading invalid data or in the disruption of the function. The described technique addresses this problem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Invalid Register Access Protection

       Described is a method that prevents a processor from
reading or writing registers in logic while the logic is per- forming
a triggered function.  Some functions of computer system logic are
triggered by setting bits in registers.  Some functions do not stop
the processor that sets the bits. Because the processor is not
stopped, there is no protection other than software convention
against the processor reading or writing registers that the logic is
using and changing. This might result in the processor reading
invalid data or in the disruption of the function.  The described
technique addresses this problem.

      For longer operations, holding a processor data bus until the
operation is complete holds up other operations. The logic must have
bits, called trigger bits, that indicate whether the logic is
performing a long-running function. The logic disallows register
reads and writes if one of the trigger bits is on (with certain
exceptions).

      If the processor attempts to read or write registers while the
logic is busy, the logic rejects a write or provides all-zero data on
a read and sets an invalid write or invalid read bit in its interrupt
status register.

      Complete blocking of writes and reads is not necessary or
desirable, though there may be other functions in the logic that
operate independently of the long-running function and that should be
available even if the scan function is busy.  In addition, the
processor must be able to check the status of the logic even if it is
busy.  The invalid read protection need not apply to control and
status registers; the processor should be allowed to read them.  It
need not apply to other registers that may be read without disrupting
the ongoing operation and that do not provide false information if
read during an ongoing operation.

      Simply not allowing reads or writes while a trigger bit is on
(but allowing the control and interrupt status registers to be read)
does not solve the whole problem.  If the processor reads the control
register while a trigger bit is on, modifies the data, and writes the
data back just after the trigger bit goe...