Browse Prior Art Database

Coordinating Fetches And Stores So As to Access Ex Lines

IP.com Disclosure Number: IPCOM000099825D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

The interaction between a processor and memory occurs both locally and globally. The architecture specifies the relationship between asynchronous processes who derive the necessary synchronization from the relative ordering of interactions between processors and memory.

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Coordinating Fetches And Stores So As to Access Ex Lines

       The interaction between a processor and memory occurs
both locally and globally.  The architecture specifies the
relationship between asynchronous processes who derive the necessary
synchronization from the relative ordering of interactions between
processors and memory.

      By witholding certain actions a processor can take advantage of
their absence and the inherent synchronization that they induce.
This can allow the processors to operate without architectural hazard
for periods of time and gain a performance advantage.

      Ordinarily, the deferral of STORE operations in a WTWAX (Write
Through Write Allocate Exclusive) L1 cache has no purpose as the line
must be held EX (Exclusive) before the store can be performed.  In
the common variant of such a hierarchy, the holding of the line EX
precludes its being accessible by any other processor.  In the
variant described below, the CORESIDENCY of EX and FWIT (Fetch
Without IOEX (Interval Of EXclusivity) Terminated) presents the
opportunity for selective action involving the deferral of STORE
operations.

      In a WTWAX memory hierarchy with multiple processors (each with
their own caches) and multiple SCE (Storage Control Element) units,
the reduction of any architectural hazard to a violation of one of
the rules associated with the proper operation of the hardware
establishes the correctness of the design.  For the System/370
architecture, hazard is represented by the observation in one or more
processors of the following sequence:
                       P1                       P2
                  FETCH B (NEW)            FETCH A (NEW)
                  FETCH A (OLD)           ...