Browse Prior Art Database

Caching the System Control Element Directories

IP.com Disclosure Number: IPCOM000099829D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 117K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

In many-way multiprocessor (MP) configurations, the requirement that System/370 architecture imposes can be satisfied by an SCE (System Control Element) design which is different from current designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Caching the System Control Element Directories

       In many-way multiprocessor (MP) configurations, the
requirement that System/370 architecture imposes can be satisfied by
an SCE (System Control Element) design which is different from
current designs.

      The SCE is assumed to be responsive to the requirement that the
processors will request lines exclusively for the purpose of changing
them.  Only one processor can hold the exclusive status, but multiple
processors can hold the line on a shared read-only basis
concurrently.  There are a range of options to choose from as regards
such a requirement. The trade-off associated with these options
attempts to balance the complexity of the SCE function and the
traffic generated to the processors in the complex.

      The simplest option actually is precluded in the class of
designs that we are considering.  This option is to have no SCE
function vis- a-vis exclusivity.  An exclusive request generated by a
processor is broadcast to all other processors forcing them to
invalidate (and cast out) the line.  As no record is maintained by
the system of which lines are currently held exclusive by any
processor, a similar broadcast action is required on each cache miss
to avoid post-hoc sharing of presumed exclusive lines.  To make this
approach viable and to eliminate the broadcast on non-exclusive cache
misses, the concept of exclusivity is dropped.  The individual caches
become STORE-THRU (WTWA or WTNWA), and the necessary architectural
precautions are taken to assure observable order.

      The second approach is based on the first.  Let the SCE
maintain a list of all the lines held exclusively by any processor.
The granting of exclusivity for a line not currently in the list is
done on a broadcast basis.  For a line in the list only the holding
processor need be affected.  Other miss requests can be handled as
appropriate without a broadcast requirement.  But it is this approach
properly extended which can provide the basis for a simpler approach
to the cache coherency problem.

      The third approach is to maintain in the SCE complete
directories of all cache lines in the MP complex.  This allows the
SCE to autonomously resolve the issues as to which processors must be
affected by any request.  It minimizes the broadcast traffic at the
expense of increasing the complexity of the SCE.

      The extension of the second option that makes it effective and
simpler than the third option is the subject of this disclosure.  The
basic idea of what follows is that in each approach the SCE maintains
something that is guaranteed to be correct with respect to finding
the item in the list when it is appropriate. However, the traffic
generated when it is not there is minimized.  Two approaches are
distinguished.  In the first, the SCE will maintain a list of all the
lines in the system that are held exclusively.  When a line not on
the list is requested exclusiv...