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Browse Prior Art Database

Foolproof Parallel Port Strobe

IP.com Disclosure Number: IPCOM000099841D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Neel, AF: AUTHOR [+2]

Abstract

This article describes a circuit arrangement wherein a computer system's power-on-self-test (POST)/basic input-output system (BIOS) determines the clock frequency, loads a value corresponding to said frequency, and a state machine in turn generates the correct timing independently of clock frequencies.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Foolproof Parallel Port Strobe

       This article describes a circuit arrangement wherein a
computer system's power-on-self-test (POST)/basic input-output system
(BIOS) determines the clock frequency, loads a value corresponding to
said frequency, and a state machine in turn generates the correct
timing independently of clock frequencies.

      The foolproof strobe circuit disclosed herein guarantees proper
minimum setup and hold times of the data strobe signal on a printer
interface.  The minimum setup and hold times are guaranteed by the
circuit which is independent of the speed at which software runs.
This will allow older software to run on machines with faster
processors.  A programming interface that eliminates the software
timing loop will make new code more efficient.

      Fig. 1 is a simplified block diagram of the foolproof strobe
circuit of this disclosure.  The key elements of this design are a
programmable strobe timer register, an eight-bit counter that
measures both the setup and the hold times, and a state machine that
governs the strobe line.

      The length of the setup and hold times must be identical and
are programmed by a value written to the strobe timer register.  A
timing value, which is machine-dependent, is written to the strobe
timer register once during power-on by BIOS.  Setup and hold times
specified for the printer interface are 0.5 microsecond.

      The eight-bit counter is loaded with the value from the strobe
timer register whenever the state machine described below enters a
pulsehigh state (setup) or a pulselow state (hold).  It is a count-
down counter that stops when it reaches zero.  A decode of the zero
state signals whether or not the counter is active.

      The state machine comprised of four set/reset fli...