Browse Prior Art Database

Data Integrity of Eeprom Data During Power Up/Down Cycles

IP.com Disclosure Number: IPCOM000099847D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Paranjape, MS: AUTHOR

Abstract

The Electrically Erasable Programmable Read-Only Memory (EEPROM) technology provides the best of the RAM and the ROM world. It allows in-circuit changes and provides data retention after power has been turned off. A typical use of this EEPROM technology is to store the microcode and the data for a microprocessor. In this application, the control signals are provided by the microprocessor (Fig. 1).

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Data Integrity of Eeprom Data During Power Up/Down Cycles

       The Electrically Erasable Programmable Read-Only Memory
(EEPROM) technology provides the best of the RAM and the ROM world.
It allows in-circuit changes and provides data retention after power
has been turned off.  A typical use of this EEPROM technology is to
store the microcode and the data for a microprocessor.  In this
application, the control signals are provided by the microprocessor
(Fig. 1).

      During a power-up or -down sequence, the control lines between
the processor and the EEPROM pass through an indeterminate state for
a finite amount of time.  This happens twice during the sequencing,
once when the +5V power is ramping up and when the POR signal goes
inactive after +5V power is up and stable.  The indeterminate state
duration is long enough for the EEPROM to interpret the command
incorrectly and begin a write operation. Once the write operation
starts, there are no external controls to stop it, causing a serious
problem of data integrity.  Since the EEPROM and the processor share
the same +5V power supply, any preprocessing of control signals is
not possible and cannot be done when the power is being cycled up or
down.

      Readily available off-the-shelf components are used to solve
the problem.  The use of a relay driver and shift register is shown
in Fig. 2.  The relay driver has a special property that its output
stays "guaranteed inactive" during a power up/down cyc...