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Communication Bus Transmitter Providing Bus-Fault Analysis

IP.com Disclosure Number: IPCOM000099861D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Goldberg, WD: AUTHOR [+2]

Abstract

This article describes a circuit arrangement and method for use in an automotive vehicle technician terminal which provides the capability to diagnose faults on a communication bus, such as shorts to ground, shorts to supply and open circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Communication Bus Transmitter Providing Bus-Fault Analysis

       This article describes a circuit arrangement and method
for use in an automotive vehicle technician terminal which provides
the capability to diagnose faults on a communication bus, such as
shorts to ground, shorts to supply and open circuits.

      New requirements occur frequently for the technician terminal
and its vehicle communication link called the assembly line data link
(ALDL).  One such requirement is to interface between the existing
ALDL input and a new communication bus named the entertainment and
comfort (E&C) bus.  Redesign of the ALDL function inside the
technician terminal and repopulating the field is not a desirable
solution.  One of the requirements is to diagnose faults on the E&C
bus, such as shorts to ground, shorts to supply and open circuits.
This is accomplished using the circuitry disclosed herein.  In
addition, this design lends itself to an implementation which
requires an external adapter to provide this new function, such as
the case with the E&C bus.

      The communication bus transmitter circuit which performs the
function of diagnosing the bus condition is shown in Fig. 1.  The
normal mode of data transmission is accomplished by setting input B
to a high state, and placing the data (inverted) on input A.  To
utilize the diagnostic function of the circuit, three tests are
performed, as shown in Fig. 2 which is a test, response and
indication table. During Test #1, a logic high level is applied to
input A and a logic low level is applied to input B.  With input A=1,
transistor Q1 is turned on.  With input B=0, transistor Q2 is turned
off.  In this case transistor Q3 is on.  Per Fig. 2, if the
communication bus is open, shorted to ground, or alright, the output
Z will be a logic zero (0).  If the communication bus is shorted to
Vss, the output Z will be a logic one (1) since the parallel
combination of R and R1 is <<R2.  In the case of a bus short to
Vss, Q3 is prevented from damage by D1.  Fig. 3 is a bus condition
diagnosis flow chart.  From Fig....