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Hardware Bring-Up Tool Using a LSSD Scanning Technique Coupled With Dynamic Memory Functions

IP.com Disclosure Number: IPCOM000099869D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 9 page(s) / 351K

Publishing Venue

IBM

Related People

Dodds, SD: AUTHOR [+6]

Abstract

This article describes a bring-up tool (BUT) that uses a level sensitive scan design (LSSD) and support circuitry for dynamic memory functions that allows for non-destructive debug of a logic card.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 22% of the total text.

Hardware Bring-Up Tool Using a LSSD Scanning Technique Coupled With Dynamic Memory Functions

       This article describes a bring-up tool (BUT) that uses a
level sensitive scan design (LSSD) and support circuitry for dynamic
memory functions that allows for non-destructive debug of a logic
card.

      Very large-scale integration (VLSI) semiconductor chips can be
tested through pattern-scanning techniques.  The technique used in
this system is LSSD.  The technique involves stringing all the
latches in a chip into a shift register. With appropriate controls,
data patterns can be shifted serially into the chip to effect chip
tests.  The LSSD control interface is made use of by the BUT such
that, with very little added, the tool is able to scan data patterns
in and out of the chip during the debugging phase of the chip's
development.  In this way, the designer gains visibility of the
states of internal chip facilities as he is tracking down a problem.
Similarly, he is able to modify states in internal chip facilities
while tracking a problem.

      The BUT also is able with hardware assist to read and write
memory locations.  It is able to do these and other functions while
maintaining the state of the machine under test.  In this system the
BUT control program runs in a personal computer.  It interfaces to
the system under test via a hardware interface card that can
manipulate the control lines and sample the state of a "clocks
stopped" status line.

      The BUT disclosed herein is used in a system shown in block
diagram in Fig. 1.  The BUT support hardware is resident in the
microprocessor storage (MPS) chip.  This chip also contains the clock
generation and control logic, and the memory controller logic.
Having all three of these units in the same chip is convenient
because there is a great deal of interaction between them.  The BUT's
scanning function takes place with system clocks stopped.  One set of
clocks, however, must remain free running.  These are clocks having
to do with the refresh of the dynamic memory arrays. This ensures
that refreshes take place, thereby preserving the state of memory
data, while the BUT is executing its functions.  Since both the BUT
memory functions and refresh deal with the same resource, it must be
ensured that both activities can take place without interference.
Interlocks were created to accomplish this.

      To effect a BUT memory access operation, the BUT control
program will scan in the appropriate control latches in the MPS chip,
includ ing memory address and data, if applicable.  The clocks in the
MPS chip will be free run for the duration of the storage operation,
at which time the BUT support hardware will stop the clocks again and
notify the BUT control program that the clocks have been stopped,
signifying the end of the storage operation.  While the clocks are
momentarily free run, it must be ensured that the system clocks to
the rest of the system are...