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Cmos Compatible Bicmos Logic Circuits With Maximized Base Drive

IP.com Disclosure Number: IPCOM000099879D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

Performance is improved in certain bipolar complementary metal oxide silicon (BICMOS) logic circuits by driving the output signal with bipolar emitter followers having base drive maximized during signal transients and base-emitter voltage (Vbe) limited by field-effect transistors (FETs).

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Cmos Compatible Bicmos Logic Circuits With Maximized

Base Drive

       Performance is improved in certain bipolar complementary
metal oxide silicon (BICMOS) logic circuits by driving the output
signal with bipolar emitter followers having base drive maximized
during signal transients and base-emitter voltage (Vbe) limited by
field-effect transistors (FETs).

      Referring to the figure, output from CMOS logic circuit 2 is
driven by NPN transistor T2 and PNP transistor T4. P-type FET T6 acts
as a time-varying resistive connection between emitter and base of
transistor T2 to limit Vbe after an initial fast rise in an output
pulse from logic circuit 2 applies maximum drive potential to the
base of transistor T2.  N-type transistor T8, which is always biased
on, is part of a high-pass RC filter (R of the transistor and gate
drain capacitance C2) turning on while the output pulse is rising
rapidly. Schottky diode D2 prevents forward biasing a diffusion in
transistor T8.

      Output pulses of opposite polarity from logic circuit 2 are
similarly driven by transistor T4 having N-type transistor T10
holding Vbe of transistor T4 low after the initial voltage swing.
P-type transistor T12 is constantly on and, with capacitance C4,
further inhibits transistor T10 turn-on during the voltage transient.
 Schottky diode D4 prevents forward biasing a diffusion in transistor
T12.