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Non-self-aligned Symmetrical Npn Transistor

IP.com Disclosure Number: IPCOM000099884D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 165K

Publishing Venue

IBM

Related People

Isaac, RD: AUTHOR

Abstract

A technique is described whereby non-self-aligned symmetrical NPN transistors are fabricated using low temperature epitaxy (LTE) boron-doped silicon for both the intrinsic and extrinsic bases. By using the intrinsic base layer for connecting the intrinsic and extrinsic bases, the transistors are made nearly symmetric. This configuration minimizes the extrinsic base capacitance, thereby producing high density, high performance NPN transistors.

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Non-self-aligned Symmetrical Npn Transistor

       A technique is described whereby non-self-aligned
symmetrical NPN transistors are fabricated using low temperature
epitaxy (LTE) boron-doped silicon for both the intrinsic and
extrinsic bases.  By using the intrinsic base layer for connecting
the intrinsic and extrinsic bases, the transistors are made nearly
symmetric.  This configuration minimizes the extrinsic base
capacitance, thereby producing high density, high performance NPN
transistors.

      Generally, parasitic capacitances which reduce the performance
of bipolar transistors can be minimized by fabricating a symmetrical
transistor, where the emitter area is identical to the collector
area.  A true symmetrical device would have the collector and the
emitter defined geometrically similarly.

      Symmetrical transistors have been proposed which define the
transistor region.  They have been fabricated by etching away the
silicon around a pedestal, which then becomes the active transistor
area.  However, the fabrication requires a diffusion step to provide
an adequate base contact and thereby increases the collector-base
capacitance.  The concept described herein eliminates this diffusion
step by providing a method of fabricating the intrinsic base layer as
a link between the intrinsic and the extrinsic bases. This link is
performed over oxide so as to produce a transistor that is nearly
symmetrical, limited only by alignment tolerances.  Since the epi
level is reduced, the extrinsic base capacitance is minimized,
thereby producing a high density, high performance transistor.

      A nine-step process is described as follows:
          The first step in the process of fabricating a non-self-
aligned symmetrical NPN transistor is to form the n+ sub- collector
and the n-epi, in the usual manner, on a p-substrate and prepare the
isolation, such as a poly-filled trench isolation and an oxide-filled
shallow trench isolation, as shown in Fig. 1.  Any features required
are fabricated, as needed, such as resistors, reach-throughs, etc.
          The second step in the process involves the depositing of
the intrinsic base layer with boron-doped LTE to the desired
thickness and doping level.  If desired, the layer can be used as a
high-value resistor since it will form a poly layer over oxide or a
single crystal layer on insulating silicon.
          The third step involves depositing a thin insulating layer
which can be tetra-ethyl-orthosilicate (TEOS), low temperature oxide,
plasma nitride, etc.  The purpose of this film is to act as an
etch-stop so that the thickness will be determined by the etch-rate
ratio.  The film may be as thin as 10 to 30 nm and patterned with
a masking step to be slightly larger than the intended transistor, as
shown in Fig. 2.
          In the fourth step, the extrinsic base is deposited with
boron-doped LTE to the desired thickness and doping level,...