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High-Density, Folded DRAM Cell

IP.com Disclosure Number: IPCOM000099888D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+3]

Abstract

This article describes a new high-density folded DRAM (dynamic random- access memory) cell. The cross section of this folded DRAM cell is shown in Fig. 1 together with its schematic layout (shown in Fig. 2). The storage capacitor is stacked and positioned over a conventional planar field-effect MOS transistor. The arrangement of the folded storage capacitors and transfer devices is different from that of the conventional planar and trench DRAM cells. By placing the storage capacitor in a stacked position over the transfer device, the cell area can be reduced and capacitance can be adjusted and improved by controlling the thickness of polysilicon.

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High-Density, Folded DRAM Cell

       This article describes a new high-density folded DRAM
(dynamic random- access memory) cell.  The cross section of this
folded DRAM cell is shown in Fig. 1 together with its schematic
layout (shown in Fig. 2).  The storage capacitor is stacked and
positioned over a conventional planar field-effect MOS transistor.
The arrangement of the folded storage capacitors and transfer devices
is different from that of the conventional planar and trench DRAM
cells.  By placing the storage capacitor in a stacked position over
the transfer device, the cell area can be reduced and capacitance can
be adjusted and improved by controlling the thickness of polysilicon.

      A process sequence for folded DRAM cells is as follows:
      (1) On a wafer with p- epi on a p+ substrate, pattern and grow
recessed field oxide (ROX) to define active area (Fig. 3).
 (2) Grow the thin gate oxide.  Then deposit and pattern CVD
npolysilicon or polycide to form a transfer gate and word line.
   (3) Implant n+ dopant (phosphorous or arsenic) to form source/
drain regions.
   (4) Blanket deposit a BPSG layer.  Open contact holes to MOS
device source/drains, fill with conductive material, and planarize
the surface.  Deposit and pattern a conductor layer (it can be first
level metal or second level polysilicon or polycide).  One
source/drain electrode of each cell transfer device is connected to a
hit line.  The other source/drain electrode is connected to...