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Asynchronous Clock-Switching Network in LSSD Methodology

IP.com Disclosure Number: IPCOM000099947D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Chan, JC: AUTHOR [+2]

Abstract

Clock switching occurs in many digital applications. For a given sequential logic design, it is often desired to switch the clock frequency asynchronously in order to operate at a different speed. Because of the inherent nature of sequential logic, clock-switching operations are prone to the hazard of glitches caused by unpredictable clock transitions. This hazard can result in failures of synchronization between the new clock and its data, or in the latching of undesired logic values into storage devices. Because clock switching is an asynchronous operation, the implementation in LSSD (Level Sensitive Scan Design) is especially difficult because of LSSD's stringent requirement on clock gating for testing reasons.

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Asynchronous Clock-Switching Network in LSSD Methodology

       Clock switching occurs in many digital applications. For
a given sequential logic design, it is often desired to switch the
clock frequency asynchronously in order to operate at a different
speed.  Because of the inherent nature of sequential logic,
clock-switching operations are prone to the hazard of glitches caused
by unpredictable clock transitions.  This hazard can result in
failures of synchronization between the new clock and its data, or in
the latching of undesired logic values into storage devices. Because
clock switching is an asynchronous operation, the implementation in
LSSD (Level Sensitive Scan Design) is especially difficult because of
LSSD's stringent requirement on clock gating for testing reasons.

      Disclosed is a new clock-switching network designed in LSSD.
Unlike the conventional edge-trigger design, this network does not
require the 'Supervising' clock, which must run at much higher
frequency, to manage the switching between two clocks.  In addition,
the clock switching network is designed to be logically hazard-free
so that the switching can occur between any two clock frequencies,
with the maximum frequency being limited only by the delay of a LSSD
latch.  The clock switching is completed by one asynchronous
triggering with minimum loss of current and new clock cycles.

      Referring to Fig. 1, the objective of the network is to select
one of the external clocks, CLK(i), upon the asynchronous triggering
by 'Switch', and then generate a set of non-overlapping clocks SC and
BC with no partial cycles or glitches during transition.

      Fig. 2 details the implementation of the 'Switch Trigger &
Clock Enable' circuit in Fig. 1.  The key to the design is the
network that generates the clock enable signal 'CLKEN' which
suppresses glitches during clock switching while minimizing the l...