Browse Prior Art Database

Programmable Microcoded Self-Test Apparatus for Processor Cache Memory

IP.com Disclosure Number: IPCOM000099954D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Campoli, LA: AUTHOR [+4]

Abstract

A solution to the problem of testing large cache memory arrays is a specialized microcode set within a central processor (CP) working with a driver program with a processor controller (PC). This solution enables the use of functional central processor hardware to test processor cache memory at machine speed, while also providing chip and cell call capability when a cache array error is detected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Microcoded Self-Test Apparatus for Processor Cache Memory

       A solution to the problem of testing large cache memory
arrays is a specialized microcode set within a central processor (CP)
working with a driver program with a processor controller (PC).  This
solution enables the use of functional central processor hardware to
test processor cache memory at machine speed, while also providing
chip and cell call capability when a cache array error is detected.

      The processor controller driver program:
(1)  initializes the test environment on the central
     processor under test;
(2)  invokes the microcode array test;
(3)  interprets the results received from the microcode; and
(4)  identifies defective array chips and cells and posts
     results.
     The central processor microcode array test:
(1)  reads and writes the array under test;
(2)  compares results;
(3)  communicates the results to the driver program in the
PC; and
(4)  is programmable using a microcode input file to allow
     different array test patterns and sequences of array
     reads and writes.
     The operation of the invention is shown in the figure.

      The operation of the microcoded cache array test begins when
the driver program is invoked from the support processor.  It loads a
microcode control file into local working store on the processor
under test.  This is the file used to "program" the microcode.  The
driver program then performs the necessary hardware initialization
and invokes the microcoded cache array test.  The microcode
interprets the file previously loaded into storage, performs the
array test, and passes the results back to the driver program. The
driver program interprets the results and identifies failing array
chips and cells if a cache array error was detected.

      The microcode control file consists of a series of commands
that define an array test.  These commands are interpreted by the
microcode in order to perform the cache array test.  Commands are
specified for:  address range, starting address, address
increment/decrement, data pattern selection, and read/write
sequences.

      The central processor hardware is used by the microcode for the
array test; no additional test hardware is needed. The hardware
characteristics necessary for a microcoded array test are:
(1)  hardware interrup...