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Dual Slope Chip Select/Deselect Driver

IP.com Disclosure Number: IPCOM000099955D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Moore, BL: AUTHOR [+3]

Abstract

The traditional use of slow-down capacitors at the base of the output drivers degrades the read performance. The disclosed technique controls the slope at the input of the output driver (output control node or NOC, see Fig. 1). Slow-down capacitors are no longer required, and the regular read access time will not be affected. The chip select receiver circuit generates NOC with dual slope for the following reasons (see Fig. 2): Slope Speed Criteria Reason 1st Fast reaches Vref-200 mv quickly Speed 2nd Slow slower dv/dt crosses Vref Output dv/dt control

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Dual Slope Chip Select/Deselect Driver

       The traditional use of slow-down capacitors at the base
of the output drivers degrades the read performance.  The disclosed
technique controls the slope at the input of the output driver
(output control node or NOC, see Fig. 1). Slow-down capacitors are no
longer required, and the regular read access time will not be
affected.  The chip select receiver circuit generates NOC with dual
slope for the following reasons (see Fig. 2):
 Slope    Speed     Criteria                       Reason
 1st      Fast      reaches Vref-200 mv quickly    Speed
 2nd      Slow      slower dv/dt crosses Vref      Output
                     dv/dt control

      The first part of the slope is accomplished by clamping the
base of transistor (T)7 with a circuit that looks exactly like Vref,
with 200 mv offset, for proper tracking with process, temperature and
power supply variation.

      The first slope is defined by an active pull-up network R4, T7.
 The second slope is defined by an RC time constant at NOC.  The RC
is made up of resistor RA and the collector to substrate capacitance,
CC5, of transistor T11. The final voltage at NOC is determined by the
RA and R7 voltage divider.

      There are two parallel current switches driven by the chip
select input.  The T3 and T4 current switch controls NOC; T6 and T5
provides the pull-down current to switc...