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Self-Aligned N And P Diffused Regions With Submicrometer Trenches

IP.com Disclosure Number: IPCOM000099957D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Lechaton, JS: AUTHOR [+2]

Abstract

Present and future VLSI circuits require complementary FET (CMOS) and bipolar transistors. These transistors require closely spaced N and P type buried layers, which are isolated from each other by trenches. Disclosed is a process for building high concentration diffused regions of both types, which are self-aligned to each other and to the isolating trenches.

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Self-Aligned N And P Diffused Regions With Submicrometer Trenches

       Present and future VLSI circuits require complementary
FET (CMOS) and bipolar transistors.  These transistors require
closely spaced N and P type buried layers, which are isolated from
each other by trenches.  Disclosed is a process for building high
concentration diffused regions of both types, which are self-aligned
to each other and to the isolating trenches.

      A solid diffusion source 2 (e.g., BSG, ASG, PSG, etc.) is
deposited with a cap 3, (e.g., Si3N4) on a silicon substrate 1,
(e.g., N epi. n on a P+ substrate).  The solid diffusion source
(layer 2) is patterned and etched to produce vertical sidewalls,
using anisotropic reactive etching.  A thin oxide layer 4 (e.g., 100
to 200 angstroms) is grown on the exposed substrate surface and a
sidewall 5 of dissimilar material (e.g., Si3N4) is formed on the
sides of diffusion layer 2. The thin oxide layer 4 is etched off the
exposed substrate surface adjacent to the sidewall.

      A second diffusion source (layer 6) is deposited over the
substrate, as shown in Fig. 2, and both dopants are driven into the
substrate approximately 0.25 to 0.4 um. Alternately, an ion implant
can replace the doping layer 6, using layers 2 and 5 as an implant
mask.  The second diffusion source (layer 6) is removed selectively
by etching and a masking oxide 7 (140 nm to 150 nm thick) is grown
on the exposed silicon surface.  The sidewall 5 is selectiv...