Browse Prior Art Database

Method for Making N And P Type Guardrings Self-Aligned to a Device Area When Using Semi-Rox Isolation

IP.com Disclosure Number: IPCOM000099959D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Mack, GL: AUTHOR [+3]

Abstract

This article relates to setting the threshold voltage of FETs and isolating devices in a CMOS or BiCMOS technology using a semi-recessed oxide (semi-ROX) field isolation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Making N And P Type Guardrings Self-Aligned to a Device Area When Using Semi-Rox Isolation

       This article relates to setting the threshold voltage of
FETs and isolating devices in a CMOS or BiCMOS technology using a
semi-recessed oxide (semi-ROX) field isolation.

      When making N channel FETs using semi-ROX isolation, the P type
surface doping 1 of the field region is usually enhanced to prevent
inversion under the thick field oxide 2.  This field-doping
enhancement is self-aligned to the device area edges by using the
device area mask 3 also as the field implant block-out mask (Fig. 1).
 Self-alignment is desired since encroachment of this doping would
affect the threshold voltage, while separation may result in
source-drain leakage.  Applying this technique to CMOS or BiCMOS
requires an additional mask 4; this blockout is used to maintain a
minimum distance 5 between the field implant and the P channel device
region 6, which is in an N type well 7.

      This article describes a method for a CMOS or BiCMOS technology
by which the device area mask 3 can be stripped selectively to the
field blocking mask 4; this permits one to implant through the
nitride 8 of the N channel region. The advantage of this is that the
threshold adjustment and background tailoring can be performed at
this relatively early point in the process, affecting only the
intended device type, and saving masking steps that would occur
later.  It is possible for the P channel FET to accomplish these same
objectives of field-doping enhancement (in the case of a P channel
FET, to prevent latch-up) and device background tailoring (including
N well formation).
      The process sequence is as follows:

      After pad oxide 9 formation and nitride 8 deposition, the
device area mask 3, 3b is formed on the wafer.  This resist 3, 3b is
hardened before the nitri...