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Browse Prior Art Database

Clock Pulse Alternator

IP.com Disclosure Number: IPCOM000099961D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 129K

Publishing Venue

IBM

Related People

Hosier, PA: AUTHOR

Abstract

Time delay block recovery time problems encountered in clock chopper design, e.g., pulse width, etc., can be reduced by the application of the clock pulse alternator scheme disclosed in this article.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Clock Pulse Alternator

       Time delay block recovery time problems encountered in
clock chopper design, e.g., pulse width, etc., can be reduced by the
application of the clock pulse alternator scheme disclosed in this
article.

      Fig. 1 illustrates the circuit block diagram of a clock chopper
clock pulse generator in which cascode blocks 1, 2, 3 and 4, which
form the disclosed Clock Pulse Alternator (CPA), generate alternate
clocks.  The clock signal Clk alternates between two time delay
blocks 5 and 6 so that each one is active every other cycle.  The
effective recovery time for each block then becomes the generated
clock pulse's deselect time, plus the entire next cycle. The CPA is
shown in more detail in Fig. 2.  Timings for the CPA may also be
found in Fig. 3.  The cascode latches 1 and 2 perform the function of
'divide by two' on the clock signal.  The 'divide by two' signal is
then used to break the clock signal up into alternate signals ClkE
and Clk0, by means of cascode logic blocks 5 and 6.  The actual
circuit schematics of these logic blocks are shown in Figs. 4 and 5.
Cascode Latches 1 and 2 pass data to each other with inversion on one
output.  The clock signal is connected to the lower level of the
latch so that data is either latched or flushed depending on whether
the clock is high or low.  The clock is connected to the latching
input on one latch and to the data side on the other latch.  Wired in
this way, one latch is always flushing data and the other is always
latched.  The single inversion of data between latches causes the
data to change in the outputs once every cycle.  This 'divide by two'
(or edge-triggered toggle circuit) generally takes six normal
single-level logic circuits to operate, so the disclosed arrangement
offers a power and density savings over practice.  Another important
aspect of its use is that it is electrically hazard-free, by design
and physical layout on chip.  This key feature allows for design
simplicity, and there is no need for additional logic blocks or
timings to guarantee that the latches will latch the correct data.

      The latch outputs are stable for an entire cycle, but because
of the latching/flushing delays, these outputs change a short time
after the clock falls (in one case) or rises (in the other case).
For this reason, it is advantageous to use the output of the latch
that latches when the clock falls, and not the lat...