Browse Prior Art Database

Software Control of Memory Performance Selection to Increase Flexibility

IP.com Disclosure Number: IPCOM000099962D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Hanna, JT: AUTHOR [+4]

Abstract

Disclosed is a method which allows software to determine the performance by which the CPU accesses memory, thus allowing the final product performance to be flexible and not constrained by the memory controller design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Software Control of Memory Performance Selection to Increase Flexibility

       Disclosed is a method which allows software to determine
the performance by which the CPU accesses memory, thus allowing the
final product performance to be flexible and not constrained by the
memory controller design.

      This disclosure describes an IBM Personal System/2 custom
memory controller gate array which interfaces the processor, DMA, or
alternate bus master to one or two single inline memory modules
(SIMMs).  The memory controller performs such tasks as generating the
memory RAS and CAS signals, coordinating the RAS and CAS address line
timing, and requesting wait states from the current bus master.

      Various speeds of memory are available.  The memory controller
must generate memory control signals so that the memory timings are
met while accounting for various system level delays.  These system
level delays include processor delay, delays through the memory
controller gate array and other planar gate arrays, capacitive signal
loading due to planar wiring, and delays due to TTL and other planar
component.

      The design of the various planar gate arrays takes place during
the early part of the development phase. Unfortunately, many aspects
that affect the timing interface between the memory controller gate
array and the memory are unknown (or rough estimates) at this point
in development. Gate array vendors may not be selected, the planar is
not laid out, delays though other planar gate arrays are tentative,
the availability of various memory speeds is unknown, and the
decision of how...