Browse Prior Art Database

Weighted Random Pattern Generation for Self-test

IP.com Disclosure Number: IPCOM000099971D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Sebastian Noecker, MC: AUTHOR

Abstract

The configuration of pseudo-random pattern self-test is described below with reference to Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Weighted Random Pattern Generation for Self-test

       The configuration of pseudo-random pattern self-test is
described below with reference to Fig. 1.

      The implementation described assumes four scan rings; however,
any number of scan rings may be used by modifying the implementation.
 Four scan rings were used because this was specifically created for
a CMOS VLSI chip.  CMOS design requirements specify that scan rings
be in multiples of four.

      Operation
1.   The pseudo-random pattern generator (PRPG), multiple input
signature register (MISR), and scan rings all operate on A/B clock
cycles.
2.   After initial seeds have been loaded into the PRPG and MISR, the
A/B clock cycle is used to generate the random patterns and to load
these patterns into the scan rings.
3.   The system clock (C clock) is used to propagate the patterns
into the logic to be tested and to capture the previous cycle's
resultant data into the scan rings. This C clock (only one cycle) is
followed by a B clock.
4.   The A/B clock cycle is run again to generate more test patterns
to be fed into the scan rings and to load the previous cycle's
resultant data into the MISR where it will be compressed and, after
sufficient test cycles have been run, will form a signature.

      The design described above is modified so that the data being
fed into the scan rings can be weighted in order to achieve higher
test coverage than that provided by prior-art pseudo-random pattern
generators.

      In order to stress the importance of using weighted patterns to
increase test coverage under certain conditions, examples will be
discussed.

      In order to obtain 100% stuck-fault coverage for the two input
gates shown in Fig. 2a, it is necessary to toggle input A and input
B, and to have output Y toggles based on the patterns applied at the
input.  The pattern shown in Fig. 2b should be sufficient to test
this gate 100%.

      To achieve this pattern set using flat random patterns would
probably not be too difficult.  However, a more complex gate is more
difficult.

      In order to obtain 100% stuck-fault coverage for this gate, it
is necessary to toggle all inputs A through H, plus have A through H
equal to one in order to toggle output Y from a 0 to a 1.
The chances of having all the inputs equal to 1 while applying flat
random patterns are slim.  The probability generating a 0 to apply to
an input as well as a 1 is 50% when using flat random patterns.
However, if the probability of generating a 1 at an input is
significantly greater than 50% when patterns are applie...