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Highly Shielded Signal Lines for MLC/MCM Carriers

IP.com Disclosure Number: IPCOM000099984D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Klink, E: AUTHOR [+4]

Abstract

A method is described of protecting and shielding critical signal lines with the support of design and wiring rules by forming a coaxial structure in a multilayer ceramic (MLC) carrier and a multichip module (MCM) environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Highly Shielded Signal Lines for MLC/MCM Carriers

       A method is described of protecting and shielding
critical signal lines with the support of design and wiring rules by
forming a coaxial structure in a multilayer ceramic (MLC) carrier and
a multichip module (MCM) environment.

      Present chip carriers are subject to electrical limitations
caused by the increased number of simultaneously switching internal
and external (on-/off-chip) switching circuits, especially fast
latches and drivers with connected loads generating high AC currents.
 These currents lead to substantial noise voltages on signal lines
and power/ ground planes.  In future ULSI chips and multichip
carriers, quiet lines in particular must be protected much more
effectively against electromagnetic disturbances and coupling.  This
becomes increasingly important at high wiring and integration
densities on multichip modules and faster circuits.

      The best way to shield critical signal lines, such as clock
lines, would be to introduce power/ground lines in the adjacent
wiring channels of such critical lines.  However, this is not
possible, since the MLC technology and EDS (electronic design system)
do not support lines in signal layers which are connected to power or
ground mesh planes. An additional limitation is that during substrate
testing, all signal lines have to be connected to power and ground.

      The method described below overcomes these limitations and
realizes the required shielding structure with the full support of
the wiring system and without breaking substrate design rules.

      Fig. 1 shows a cross sec...