Browse Prior Art Database

Dense Multi-Port SRAM Cell

IP.com Disclosure Number: IPCOM000099988D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+2]

Abstract

High-speed general-purpose registers used in the pro- cessing unit of a computer must often be multi-port RAMs, i.e., they must have n data input and output ports and n address ports (n = 2, 3, 4, ...) to perform multiple (n) store and fetch operations in a single cycle. Data, for instance, can be written via (input) port W1 into a memory cell selected by address AW1. During the same cycle, data from three other cells, each controlled by different addresses AR1, AR2 and AR3, can be read through (output) ports R1, R2 and R3, respectively. In addition, such multi-port registers must usually be fully static RAMs, i.e., the data should be stored in a static latch and the read operation should be unclocked.

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Dense Multi-Port SRAM Cell

       High-speed general-purpose registers used in the pro-
cessing unit of a computer must often be multi-port RAMs, i.e., they
must have n data input and output ports and n address ports (n = 2,
3, 4, ...) to perform multiple (n) store and fetch operations in a
single cycle.  Data, for instance, can be written via (input) port W1
into a memory cell selected by address AW1.  During the same cycle,
data from three other cells, each controlled by different addresses
AR1, AR2 and AR3, can be read through (output) ports R1, R2 and R3,
respectively.  In addition, such multi-port registers must usually be
fully static RAMs, i.e., the data should be stored in a static latch
and the read operation should be unclocked.

      For a CMOS VLSI multi-port SRAM with n I/O ports, a dense and
fast n-port memory cell is proposed which requires only 6 + n
devices:  four for the static latch used as a storage element, two
for an integrated inverting buffer, and one for each I/O port.  Such
low device count is achieved by minimizing the cell port circuitry
and attaching it to the latch in single-ended connection.

      Each read port is realized by an NFET transfer device TR, with
the source/drain being connected to a read bit line BLR and the gate
being connected to a read word line WLR. All read port devices TR are
dotted together and connected to the right latch node NC through a
single inverter serving as a common preamplifier and driver for all
read ports. Thus, instead of inserting one buffer per read port, a
single powerful inverter is provided to buffer and decouple the latch
from the high-capacitance read bit lines.

      A single-ended write scheme is adopted which allows using one
transfer device TW for each write port connected to the left latch
node NT.  The incoming data are received on a single write bit line
BLW (for each port).

      Referring to the circuit schematic and the timing diagram
(Figs.  1 and 2), the write/read operation of a four-port cell, for
example, is as follows:

     ...