Browse Prior Art Database

Fast On-Module Driver/Receiver Scheme

IP.com Disclosure Number: IPCOM000099992D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+3]

Abstract

The cycle time of a CPU is determined by, among other things, the delay of the cache and the address generation paths which include slope-controlled off-chip bidirectional driver/receiver circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Fast On-Module Driver/Receiver Scheme

       The cycle time of a CPU is determined by, among other
things, the delay of the cache and the address generation paths which
include slope-controlled off-chip bidirectional driver/receiver
circuits.

      The delay of such a driver/receiver circuit cannot be reduced,
as
      1.   the output slope of the driver must be controlled to
comply with the simultaneous switching rule (SWR), i.e., to allow a
large number of simultaneously switching drivers, and
      2.   the receiver requires a high noise tolerance.

      These requirements are due to the high module/chip inductance,
i.e., the inductance between the module ground pin and chip ground
and the inductance of the power lines on the multichip module (MCM).
The driver deltaI/deltat causes ground (G) and power (VH) noise.

      A bidirectional driver/receiver circuit must also support a
self-test and an interconnection test.  These tests require
multiplexers (MUXs) which are driven by the slave outputs (true and
complement) of the boundary scan latch and gated by a control signal
BSC. The conventional tristate driver TSD usually has a high
impedance (HZ) and ten-speed line inputs for I/O slope control.

      The design of an off-chip driver and the SWR are determined by
the above-mentioned ground and power line inductances.  The novel
driver/receiver scheme described in this article implements for an
MCM not only a conventional off-chip (o...