Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Diagonal Wiring Direction for VLSI Logic Chips With Three Wiring Layers

IP.com Disclosure Number: IPCOM000099997D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Anderson, HW: AUTHOR [+4]

Abstract

The size of VLSI logic chips is determined by the required number of wiring channels. Prior-art chips have two layers with about 2000 horizontal and vertical channels each. Further wiring layers permit smaller chips but pose technical problems. a. With three layers, the third layer is used in the same direction as the first. The ratio of horizontal to vertical channels is 2:1. In many cases, the facilities available in one direction cannot be utilized in full. b. With four layers, the channel facilities are symmetrical, but the manufacturing process is highly complex and thus very expensive. c. The complexity of the chip's topology increases with each layer, leading to greater channel spacings.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Diagonal Wiring Direction for VLSI Logic Chips With Three Wiring Layers

       The size of VLSI logic chips is determined by the
required number of wiring channels.  Prior-art chips have two layers
with about 2000 horizontal and vertical channels each. Further wiring
layers permit smaller chips but pose technical problems.
      a.   With three layers, the third layer is used in the same
direction as the first.  The ratio of horizontal to vertical channels
is 2:1.  In many cases, the facilities available in one direction
cannot be utilized in full.
      b.   With four layers, the channel facilities are symmetrical,
but the manufacturing process is highly complex and thus very
expensive.
      c.   The complexity of the chip's topology increases with each
layer, leading to greater channel spacings.  For example,
           3 mm           1st layer
           4 mm           2nd layer
           5 mm           3rd layer

      Wiring programs demand uniform spacings in the first and the
third layer, e.g., 5/4/5 mm or 3/4/6 mm.  In such a case, the
technological facilities are not utilized in full.

      For large VLSI chips, the line resistances may rise to kL
values.  The wiring capacitances are in a range of up to 10 pF.
Thus, the RC time constant of the lines is of the order of the
switching times of CMOS transistors.  Line resistances mean higher
switching times for very...