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Three-Phase Design Approach for VLSI Chip

IP.com Disclosure Number: IPCOM000099999D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Najmann, K: AUTHOR

Abstract

A design approach is described which permits the partial wiring of VLSI chips of any size in the logic design phase.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Three-Phase Design Approach for VLSI Chip

       A design approach is described which permits the partial
wiring of VLSI chips of any size in the logic design phase.

      The proposed approach takes account of the fact that relatively
accurate data on the entire logic are available at a very early stage
of logic design.  In addition, the logic designer knows how the
individual elements of the logic interact and are to be wired.

      This knowledge permits the production of a "global chip" in a
first phase.  In such a chip, the individual logic elements, which
are unwired except for the global lines integrated or terminating in
them, may be placed in an optimum fashion, since at this stage there
are no important schedules that might be affected.

      The chip designer knows the basic structure of the logic which
consists of individual logic elements (regions), such as control
logic, adder, etc., and macros, if any.  He also knows the
approximate number of circuits required for each logic element, the
size of the macros, the required number of connecting lines between
the individual elements and the macros, as well as the connectors to
the chip I/Os.

      The designer knows roughly whether the circuit fits the
predetermined chip area.  In addition, he is able to say how many
individual basic elements, i.e., cells, are required for the
individual logic elements.

      In summary, the following information is available to him:
      1.   the chip size and the number of cells
      2.   the number of logic elements (regions)
      3.   the number of cells in each region
      4.   the number and size of macros
      5.   the number of connections between logic macros and
           I/Os. On the basis of this information, the required chip
may be globally designed with optimum wiring between the individual
regions.  This physi...