Browse Prior Art Database

Structured Custom Layout

IP.com Disclosure Number: IPCOM000100012D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Buettner, S: AUTHOR [+3]

Abstract

A fast layout method for CMOS VLSI logic circuits is proposed which maintains full customization of the devices and allows flexible placement. Custom design is required for performance and area optimization.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Structured Custom Layout

       A fast layout method for CMOS VLSI logic circuits is
proposed which maintains full customization of the devices and allows
flexible placement.  Custom design is required for performance and
area optimization.

      A structured layout is obtained by device stacking in a
predetermined direction, using a symbolic layout (stick diagram)
technique.  The final graphics implementation (GL1 data) is done by
repeated copying of a standard device layout, followed by vector
shifting for customization.

      This method is particularly suitable for the peripheral (logic)
circuitry of an embedded array macro, as it meets the turn-around
time, area and performance requirements.

      The objective is to place and wire a fully customized circuit
in a given area with a predetermined aspect ratio.

      Fig. 1 shows a 2-input NAND gate as an example of a logic
circuit required for an array macro design.  The gate, comprising two
parallelconnected P transistors T1, T2 and two series-connected N
transistors T3, T4, has two inputs IN1, IN2 and an output OUT and is
arranged between potentials VH and GND.  The wiring is placed in two
metallization layers M1, M2 (Fig. 3).  The circuit must be arranged
as shown in Fig. 2.

      The procedure to be used is as follows:
      1)   Determine the appropriate direction for device stacking
according to the required aspect ratio (rectangle in Fig.  2).
      2)   Estimate t...