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Personalized Memory Array Addressing

IP.com Disclosure Number: IPCOM000100022D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 136K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR [+2]

Abstract

A method for addressing an array made of registers with prediffused devices is disclosed which has the following characteristics: - the addressing is such as to allow a wide number of registers in spite of a low predefined voltage swing between the two latch outputs, and - the addressing is such as to enable the differential sensing of the true and complement latch outputs, and is based on cascode circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Personalized Memory Array Addressing

       A method for addressing an array made of registers with
prediffused devices is disclosed which has the following
characteristics:
      -    the addressing is such as to allow a wide number of
registers in spite of a low predefined voltage swing between the two
latch outputs, and
      -    the addressing is such as to enable the differential
sensing of the true and complement latch outputs, and is based on
cascode circuits.

      An essential part of the disclosure is a novel decoder which is
a 'bit address' and a 'word address' decoding combination at the same
time. The bit address choice has an influence on the word address
decoding, as described later.

      A register is deselected by shifting down all its latch
collector output potentials, while a register is selected by keeping
all its latch collector output potentials at its standard level.

      All latches have an emitter follower stage on each output,
which is dotted to all other associated latches belonging to the same
bit, realizing an OR function. Thus, the potential at the dotted line
takes the potential as given by the selected word latch for the
considered bit. Note that there are two dotted lines (called left bit
line and right bit line) per physically implemented bit.

      The output circuit has to sense the bit line signals. In
addition, here it has to choose the convenient bit lines among a
group of bit lines, due to the bit addressing: the output circuit is
an N-way multiplexer.

      The latches are grouped two by two, four by four, or eight by
eight, etc.

      Assuming the latches are grouped two by two, and called even
and odd bit latch in a common double cell, there is 1-bit address
that will enable to choose either the even or the odd latch.

      Fig. 1 shows the logical arrangement (1-port 128 x 9
personalized array), with the WRITE Path in dotted lines. Fig. 2
shows the memory double-cell circuitry.

      As apparent from Fig. 2, the conventional 2-level cascode latch
circuitry is recognized with T1 to T7 transistors and with the XE
input for write operation in the even bit. The odd-bit circuitry is
similar.

      On top of this conventional circuitry are superposed the read
deselection currents IL and IR flowing into both collector
resistances. These currents are controlled by the decoder W (true)
and WB (complement) outputs so as to flow either into the one or the
other bit. This control is due to T8E, T9E, T80 and T90 transi...