Browse Prior Art Database

Hardware Verification Scheme Detects All Types of Diskette Data Recovery Errors

IP.com Disclosure Number: IPCOM000100027D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Reid, EM: AUTHOR [+2]

Abstract

This article describes a mechanism for performing data verification following a direct-access storage device (DASD) write operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Hardware Verification Scheme Detects All Types of Diskette Data Recovery Errors

       This article describes a mechanism for performing data
verification following a direct-access storage device (DASD) write
operation.

      Current hardware-based verification techniques are incapable of
detecting certain types of diskette data errors.  This article
describes a hardware implementation capable of detecting all types of
diskette data recovery errors.

      The traditional data verification technique relies on a cyclic
redundancy check (CRC) to detect data errors.  This technique is
incapable of detecting errors which can occur in the following
situations:
      1)   Data is corrupted before it reaches the floppy disk
controller (FDC), causing CRC to be generated on the corrupted data,
      2)   A hardware fault prevents data from actually being written
to the diskette, but the CRC check bytes remain valid for the data
previously written on the media.

      To avoid these limiting data, a buffer can be modified so that
a true byte-by-byte comparison is performed in hardware "on the fly"
in the same amount of time required to perform the traditional
hardware verify operation.  This special verify mode can be
implemented by adding a byte comparator to the data buffer and
modifying the data buffer control logic (read and write pointers) so
that data comparison can be performed between the data buffer and the
floppy read data bus, as shown in...