Browse Prior Art Database

Metastability Proof Latch

IP.com Disclosure Number: IPCOM000100047D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 104K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

Disclosed here is a circuit configuration which combats the susceptibility of digital latches to metastable conditions. In asynchronous systems, there are certain instantances when noise spikes or glitches are generated due to two signals changing at approximately the same time. Such glitches can be large enough to insert a small packet of energy into a latch and cause it to become metastable. The metastability manifests itself in either of two ways: it either causes the latch to go into oscillation due to its feedback loop or causes the latch output to produce an indeterminate voltage level. In either case, once started, the metastable condition exists for an indeterminate length of time before it settles out and usually causes eratic hardware failures.

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Metastability Proof Latch

       Disclosed here is a circuit configuration which combats
the susceptibility of digital latches to metastable conditions. In
asynchronous systems, there are certain instantances when noise
spikes or glitches are generated due to two signals changing at
approximately the same time.  Such glitches can be large enough to
insert a small packet of energy into a latch and cause it to become
metastable.  The metastability manifests itself in either of two
ways:  it either causes the latch to go into oscillation due to its
feedback loop or causes the latch output to produce an indeterminate
voltage level.  In either case, once started, the metastable
condition exists for an indeterminate length of time before it
settles out and usually causes eratic hardware failures.

      Some simplifying assumptions are used to reduce the scope of
the problem.  The first assumption is that it does not matter whether
glitches set the latch or leave it undisturbed, just as long as the
latch does not go metastable.  In most cases either stable result is
acceptable and can be dealt with logically in a predefined manner.
The next assumption is that the two signals which can cause
metastability (usually data and clock) are logically "ANDed" together
such that glitches can only occur when both signals are logical ones
simultaneously.  Finally, the "AND" of the two signals is used only
to set the latch. Once set, the latch will be reset through an
entirely separate path based on a reset signal (-RESET), whose timing
is shown in the figure.

      Key to the metastability solution is the standard digital logic
circuit called the Schmitt trigger (ST).  The figure shows the
interconnection recommended between two Schmitt triggers, OR gate 1
(OR1), and three AND gates (A1, A2, and A3) to form a Level Sensitive
Scan Design  (LSSD) dual latch composed of L1 and L2 latch stages.
The ST varies slightly from the standard inverter element in that it
has two unique thresholds:  an upper and a lower.  A signal being
input, the ST must rise above the upper threshold to cause the output
of the ST to change state (go to a down level).  Likewise, a falling
input signal must drop below the lower threshold to cause the ST
output to change state (go to an up level).  Since there is a
difference between upper and lower levels, a Schmitt trigger tends to
be a pulse stretcher, and it is used as such in this discl...