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Low Stress Structures for Cooling Large Area Silicon

IP.com Disclosure Number: IPCOM000100066D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 29K

Publishing Venue

IBM

Related People

Horton, RR: AUTHOR [+5]

Abstract

Silicon substrates for semiconductor use are fragile. A solution to minimize stresses induced when cooling large area silicon substrates is to attach multiple individual cooling structures. As the sum of each of these constrained areas is less than the total surface area, the net stress acting on the wafer will decrease.

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Low Stress Structures for Cooling Large Area Silicon

       Silicon substrates for semiconductor use are fragile. A
solution to minimize stresses induced when cooling large area silicon
substrates is to attach multiple individual cooling structures.  As
the sum of each of these constrained areas is less than the total
surface area, the net stress acting on the wafer will decrease.

      A matrix of tubular structures having a number of through holes
to increase exposed area is attached to the back of the large area
silicon substrate by a thermally suitable technique, such as solder
reflow or by using a conductive polymer.  This configuration has been
measured to have a thermal resistance of 1.8 C/watt in an air flow of
1 m/s.  It is possible to dissipate 20 watts given a junction-to-box
temperature drop of 36 degrees centigrade.