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Termination Circuitry for Multiple Differential Clock Copies

IP.com Disclosure Number: IPCOM000100072D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Baumgartner, SJ: AUTHOR [+4]

Abstract

The figure illustrates a use of BIPOLAR technology which allows a variable number of differential clocks to be distributed within tight timing specifications without turning off the unused clock copies.

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Termination Circuitry for Multiple Differential Clock Copies

       The figure illustrates a use of BIPOLAR technology which
allows a variable number of differential clocks to be distributed
within tight timing specifications without turning off the unused
clock copies.

      A current source for each differential pair is represented by
Q7 and R3.  This current is controlled by an OPAMP's feedback loop.
A 2.5 Kohm external resistor allows for amplitude programming and
provides temperature and process compensation.  IN+ and IN- drive
bases of Q5, Q6, Q8 and Q9 which represent 10 differential pairs.
Each of the differential outputs, PSYNCx and NSYNCx (x=0 to 9), has a
set of external 80-ohm pull-up resistors represented by R4, R5, R6
and R7.  These are located adjacent to the output pins.  Each clock
pair is then distributed on the main board by equal-length wires, one
pair to each card slot. Eighty-ohm pull-down resistors, represented
by R8, R9, R10 and R11, are placed on receiving cards.  These are
used to set clock levels compatible with the "TTL like" differential
receivers.  Thus, if a card exists in any of the card slots, those
particular nets are terminated.  All the empty slots are
unterminated.

      In the case of RECEIVING CARD 0, PSYNC0 and NSYNC0 are
terminated.  Therefore, with 12 mA in the current source of the
output driver, PSYNC0 and NSYNC0 swing between 1.8 and 1.3 volts.  If
Q5 is on and Q6 is off, NSYNC0 pulls up to 1.8 volts due t...