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Clock Distribution Method

IP.com Disclosure Number: IPCOM000100076D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Baumgartner, SJ: AUTHOR [+5]

Abstract

Fig. 2 illustrates a crystal oscillator driving a CLKA module at a base frequency f. The CLKA module outputs 10 copies of a differential synchronous signal at frequency f with a single-ended signal having an up level of 1.8 volts and a down level of 1.3 volts. This signal is called the SYNCH pulse.

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Clock Distribution Method

       Fig. 2 illustrates a crystal oscillator driving a CLKA
module at a base frequency f.  The CLKA module outputs 10 copies of a
differential synchronous signal at frequency f with a single-ended
signal having an up level of 1.8 volts and a down level of 1.3 volts.
 This signal is called the SYNCH pulse.

      A CLKB module resides on each card in a system.   A
phase-locked loop (PLL) inside each CLKB receives one of the 10
differential CLKA outputs.  A VCO operating at 4*f inside CLKB is
divided by 4, generating two signals which are ninety degrees out of
phase along with their inverses. These signals are called CLKW, CLKX,
CLKY, and CLKZ signals, as shown in Fig. 1.  These four signals are
repeated 4 times and driven off-chip by a CLKB output driver.  The
CLKB outputs are TTL compatible.

      One of the CLKW signals and a corresponding CLKY signal are
wired to PLL feedback inputs as well as to receiver modules.  The
CLKB PLL compares the CLKW and CLKY signal to the SYNCH pulse and
adjusts the CLKW and CLKY until their phase and frequency match that
of the SYNCH pulse.  Since the SYNCH pulses arrive at the same time
to each CLKB module and each CLKB module has the same PLL, the CLKW,
CLKX, CLKY and CLKZ transition occur at the same time on all cards.