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Browse Prior Art Database

Improved Clock Tolerance by Using Common Oscillator Transitions

IP.com Disclosure Number: IPCOM000100079D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+3]

Abstract

Described is a method to generate tight tolerances between clocks on a system processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 79% of the total text.

Improved Clock Tolerance by Using Common Oscillator Transitions

       Described is a method to generate tight tolerances
between clocks on a system processor.

      A bipolar logic chip is used to generate four oscillator
signals.  Each oscillator signal has a 50% duty cycle and is shifted
in phase by 1/4 cycle, as shown in Fig. 1.  All processor logic chips
receive the four oscillator signals.  The four oscillator signals are
used on chips to internally generate all required clocks.  The
internally generated clocks are used for latches, arrays, and enable
inputs to drivers.  The internally generated clocks have duty cycles
of 1/4, 1/2, or 3/4 and start on any quarter cycle boundary.  Tight
tolerance is required between all transitions of all clocks,
including a clock to itself, to achieve high system performance.

      Process parameters, temperature, and power supply affect rising
oscillator generation logic differently than falling oscillator
generation logic.  For this reason, specified tolerances on
oscillator inputs are better between common transition edges
(rise-rise or fall- fall) than opposite transition edges (rise-fall
or fall-rise).  Fig. 2 lists the tolerances between all combinations
of oscillator transitions in the design.

      Only rising transitions of oscillator inputs are used to
generate rising and falling clock edges on this design. Limiting
usage to a common transition from all oscillator inputs prevents
sloppy tolerances...