Browse Prior Art Database

Sub-Fru Check Masking of Power Boundaries

IP.com Disclosure Number: IPCOM000100091D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR [+2]

Abstract

A single FRU (Field Replaceable Unit) has two power boundaries - some of its logic runs on one power supply, and some of its logic runs on another power supply. A single check bit summarizes hardware failures from anywhere in the FRU. This check bit must not turn on spuriously when one of the power supplies is turned off.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Sub-Fru Check Masking of Power Boundaries

       A single FRU (Field Replaceable Unit) has two power
boundaries - some of its logic runs on one power supply, and some of
its logic runs on another power supply.  A single check bit
summarizes hardware failures from anywhere in the FRU.  This check
bit must not turn on spuriously when one of the power supplies is
turned off.

      This invention avoids spurious check conditions by masking off
those checkers that come from the other power boundary when its power
is off.

      The figure shows how this invention works.  It is composed of
the following components:
 1.  FRU (Field Replaceable Unit).  This is the smallest unit that
can be replaced in the field when something breaks.  The check
register bits are designed to indicate which FRU contains the error.
 2.  Power boundary One.  This area is one of the two power
boundaries on this FRU.
 3.  Power boundary Two.  This area is the other power boundary on
this FRU.  Power to the logic within this boundary may or may not be
"good" during logical operation of the machine.  When it is not
"good", the logic may behave in a random fashion, and may activate
check logic spuriously, even though no hardware failure is present.
 4.  Checkers on power boundary one.  These circuits detect hardware
failures on the first power boundary of the FRU.
 5.  OR gate.  Summarizes the results of the checkers on the second
power boundary.  In an alternative embodiment, each checker 10 could
directly connect to a separate AND gate 6 for...