Browse Prior Art Database

System Performance Improvement by Use of Enhanced Service Bus Interface Architecture

IP.com Disclosure Number: IPCOM000100104D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 156K

Publishing Venue

IBM

Related People

Burmeister, WF: AUTHOR [+3]

Abstract

Disclosed is an enhanced Service Bus Interface archi- tecture that provides significant improvements in system performance. The described architecture includes hardware specifically designed to handle the operations that typically occur on the Service Bus. By allowing hardware to handle the operations, they not only occur more quickly, but also relieve much of the burden on the Support Processor, allowing for greater total system throughput.

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System Performance Improvement by Use of Enhanced Service Bus Interface Architecture

       Disclosed is an enhanced Service Bus Interface archi-
tecture that provides significant improvements in system performance.
 The described architecture includes hardware specifically designed
to handle the operations that typically occur on the Service Bus.  By
allowing hardware to handle the operations, they not only occur more
quickly, but also relieve much of the burden on the Support
Processor, allowing for greater total system throughput.

      In System/370 systems, the Service Bus Interface is the means
through which the Service Processor communicates with the main
processor.  The interface is a serial bus comprised of five signal
lines:  Data In, Data Out, Shift, Set and Mode.  In typical
System/370 implementations, the control of these lines is almost
completely accomplished by individually controlling the five output
lines with micro- computer instructions.  The content and rates of
change of these lines are handled totally by programming, and tend to
consume the power of the Service Processor whenever the process is
active.  Because of the large number of primitive cycles which are
involved, the resultant bit transfer rate is often substantially less
rapid than the target hardware can accept.

      The Enhanced Architecture adds an Auto Mode that includes the
enhancements, but also allows a Manual Mode for emulation of the
existing Service Bus Interface architecture.

      The Enhanced Service Bus Interface architecture requires the
following:
      Nine-Bit Data Register (8 Data + 1 Parity Bit),
      Count Register,
      Control/Status Register and
      Parity Generator/Checker.
      These items are shown in the drawing.

      To provide compatibility, the implementation continues to
permit support of the individual states of all five service interface
lines.  This allows older SP software implementations which
individually control the lines to be used.

      The automatic mode implementation allows transmission and
control of data to be more easily and rapidly specified and combines
efficiency and speed improvements with less complicated SP
programming.

      The Control/Status Registers have been implemented as a single
register.  When the register is written to, it is interpreted as a
Control Register, and when it is read from, it may be interpreted as
a Status Register.

      The Data Register is implemented as a nine-bit shift register.
The register is readable and writeable.  In addition, hardware is
available that will generate the correct parity for the eight bits in
the Data  Register such that it may be written into the ninth or
Parity Bit.  This operation is initiated by the Control Register.
Additionally, hardware will also check that the contents of the
Parity Bit of the register matches the value of the correct parity
for the eight bits of data i...