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Overlap Signal Generation Circuit

IP.com Disclosure Number: IPCOM000100111D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Chu, AM: AUTHOR [+4]

Abstract

A new overlap signal generator circuit is used which has fewer transistors and therefore less parasitic capacitance than the conventional combination of an AND and an OR complementary metal oxide silicon (CMOS) circuit. Thus, delays are shorter in the new CMOS circuit.

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Overlap Signal Generation Circuit

       A new overlap signal generator circuit is used which has
fewer transistors and therefore less parasitic capacitance than the
conventional combination of an AND and an OR complementary metal
oxide silicon (CMOS) circuit.  Thus, delays are shorter in the new
CMOS circuit.

      Referring to the timing diagram (Fig. 1) and circuit diagram
(Fig. 2), input signal IN generates a phase A signal which overlaps a
phase B signal wherein delays TB and TAB are minimal due to low
parasitic capacitance on nodes N1 and N2.  At time t0, input signal
IN and outputs A and B are low (at logic zero).  Transistors T1, T2,
T5, T6, and T10 are on while transistors T3, T4, T7, T8, and T9 are
off. At time t1, IN goes high, turning on NFETs T3 and T8 while
turning off PFETs T2 and T6.  The turn-on of transistor T3 discharges
node N1 to low which causes output A to go high.  As phase A goes
high, NFET T7 is turned on which discharges node N2 to low, causing
phase B to go high. At time t2, IN returns to low, turning on PFETs
T2 and T6 while turning off NFETs T3 and T8.  Turning on transistor
T6 charges node N2 to high, causing phase B to go low.  As B goes
low, PFET T1 is turned on which charges node N1 to high.  Phase A is
caused to go low, thus returning the circuit to its initial state.