Browse Prior Art Database

Self-Aligned Polysilicon Load Resistors

IP.com Disclosure Number: IPCOM000100125D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Koblinger, O: AUTHOR

Abstract

A process sequence is described which, by means of CMOS technology, using one additional mask, permits the simultaneous production of high-ohmic polysilicon for load resistors and low-ohmic implanted polysilicon. For this purpose, a thick oxide mask, protecting the underlying polysilicon during implantation, is produced in the desired regions of the polysilicon. This oxide mask is used as a protective means during silicidization to prevent the formed silicide, such as titanium silicide, from short-circuiting the high-ohmic resistors.

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Self-Aligned Polysilicon Load Resistors

       A process sequence is described which, by means of CMOS
technology, using one additional mask, permits the simultaneous
production of high-ohmic polysilicon for load resistors and low-ohmic
implanted polysilicon.  For this purpose, a thick oxide mask,
protecting the underlying polysilicon during implantation, is
produced in the desired regions of the polysilicon.  This oxide mask
is used as a protective means during silicidization to prevent the
formed silicide, such as titanium silicide, from short-circuiting the
high-ohmic resistors.

      The sequence proceeds from a structure (Fig. 1A) with a
polysilicon resistor mask 4 (PORE mask).  After deposition of
intrinsic polysilicon 2 on a substrate 1 and LPCVD (low-pressure
chemical vapor deposition) of nitride 3 on polysilicon layer 2, this
mask is applied to nitride layer 3.  After nitride layer 3 has been
etched by means of that mask (Fig. 1B), the remaining photoresist
mask 4 is removed (Fig.  1C).  In the subsequent polysilicon oxide
growth step, the structured nitride layer 3 serves to limit the
growth of polysilicon oxide 5 (POX) (Fig. 1D) which is formed only in
the regions where the polysilicon load resistors are to be positioned
later on.  As POX 5 is grown on the intrinsic polysilicon 2, the
cross-section of the latter is reduced, i.e., the polysilicon load
resistor may have a shorter length.  After deposition of POX 5,
nitride 3 is removed by wet etching with hot phosphoric acid or by
dry etching with CHF3/O2 (Fig. 1E).

      This is followed by blanket ion implantation (Fig. 1E), as the
thick POX 5 protects the regions of the intrinsic polysilicon
resistor.  During ion implantation, normal overlay tolerances and
bird's beak are insignificant, as the regions...