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Self-Isolating Very High Performance HBT Structure and Process for Its Realization

IP.com Disclosure Number: IPCOM000100129D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

This article describes a self-isolating gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) device structure having extremely low parasitic capacitances, and the process by which it may be realized. The disclosed device structure overcomes the need for an isolation implant, thereby reducing isolation quality concerns as well as device size.

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Self-Isolating Very High Performance HBT Structure and Process for Its Realization

       This article describes a self-isolating gallium arsenide
(GaAs) heterojunction bipolar transistor (HBT) device structure
having extremely low parasitic capacitances, and the process by which
it may be realized.  The disclosed device structure overcomes the
need for an isolation implant, thereby reducing isolation quality
concerns as well as device size.

      The disclosed HBT device structure is shown in Fig. 1. Figs.
2-8 illustrate the process employed to obtain the Fig. 1 structure.
Referring to Fig. 1, the extrinsic P+ base 18 is formed in an undoped
aluminum gallium arsenide (AlGaAs) or GaAs layer 5.  It should be
noted that this extrinsic base 18 is present only on one side of the
intrinsic P base 8.  The base contact will also be formed on this
side.  This arrangement yields a remarkable reduction in
collector-base parasitic capacitance as well as device size.

      Referring to Figs. 2-8, the involved process steps are in the
following order:
 (1) Fig. 2 ... Starting with an undoped GaAs wafer 2, and using a
photoresist (PR) mask and ion implantation, the N+ region 4 is
formed, followed by an anneal.
 (2) Fig. 3 ... A 2000-4000-angstrom thick layer of undoped AlGaAs
(or GaAs) 5 is formed on 2 by either MOCVD or MBE after which a
PR mask is used to form N regions 6 immediately above the N+ region
4.  Anneal.
 (3)  Fig. 4 ... By use of MOCVD or MBE, the following are
successively formed; N 1000 angstroms P GaAs layer [8]; N 1500
angstroms N AlGaAs layer 10; N 1000 angstroms N+ GaAs layer 12.
Optionally, a N 200-angstroms layer of InAs may be formed above 12
and then a N 2500 angstroms layer of WSi 14 may be formed at the
top, as illustrated in the figure. It may also be possible to use a
metal system other than WSi, e.g., Mo/Ge/In/W, to obtain layer 14.
(4) Fig. 5 ... An island, such as shown in the figure, may be formed
in 14 using a CF4 RIE and masking.  Retaining th...