Browse Prior Art Database

Controlling of Microprocessor's Internal And External Cache Memory

IP.com Disclosure Number: IPCOM000100146D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Leung, WL: AUTHOR [+2]

Abstract

A technique is described whereby an external cache controller is used in microprocessor computer systems to inform of the locality of storage references of internal microprocessor cache memory. The method described insures that the most referenced address lines inside the processor are not discarded from an external cache due to lack of reference.

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Controlling of Microprocessor's Internal And External Cache Memory

       A technique is described whereby an external cache
controller is used in microprocessor computer systems to inform of
the locality of storage references of internal microprocessor cache
memory.  The method described insures that the most referenced
address lines inside the processor are not discarded from an external
cache due to lack of reference.

      Generally, as technology increases the density, microprocessors
will have "small" internal cache memory. This typically does not
eliminate the need for external cache memory and proper controls.
The concept described herein provides a method whereby the
performance of the two cache memories, internal and external, can be
enhanced without impeding processor access to the internal cache.  At
the same time, the external cache will be informed of the locality of
storage references in the internal cache.  The block diagram of Fig.
1 illustrates the interfacing which takes place between the internal
cache of the processor and the use of the external cache controller
interfaced to the external cache memory device.

      In actual operation, the microprocessor will send the "cache
line address" information of the HITs produced by the internal cache
to the external cache controller.  A special signal line designated
"NO DATA NEEDED" is used to inform the external cache controller.
The special ignal is sent along with the "cache line address" to the
external cache controller and can be encoded and combined with other
control information so as to save I/O pins on the chip.

      The processor sends the "cache line address" that HITs its
internal cache out through the processors address lines only when it
is different from the previous "cache line address" so as to minimize
the traffic.  The block diagram of Fig. 2 illustrates the method used
to control the broadcasting of the HIT information.  Note that the
ADR1 register is gated only when th...