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Fast CMOS Stop_l1 Function

IP.com Disclosure Number: IPCOM000100173D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Peterson, MJ: AUTHOR

Abstract

Disclosed is a method of stopping CMOS latches without requiring a signal to propagate in one half of the machine cycle. Whenever the stop signal is asserted the data from the output of the latch is fed back to the input of the latch using circuitry already on the chip.

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This is the abbreviated version, containing approximately 100% of the total text.

Fast CMOS Stop_l1 Function

       Disclosed is a method of stopping CMOS latches without
requiring a signal to propagate in one half of the machine cycle.
Whenever the stop signal is asserted the data from the output of the
latch is fed back to the input of the latch using circuitry already
on the chip.

      CMOS chips use a signal called STOP_L1 to gate the L1 clock
into all of the chip latches to "freeze" the state of the chip for
test functions and during error situations, etc.  This function is
shown logically in Fig. 1.

      The STOP_L1 signal must be generated from L2 latches to meet
LSSD test requirements.  This signal starts with the front edge of
the L2 clock and must reach all latches on the chip before the front
edge of the L1 clock; thus, it must propagate in one half cycle.

      The fix for this problem is shown in Fig. 2.  Whenever the
STOP_L1 signal is asserted the output of the latches is fed back to
the data input.  The latches are also prevented from scanning by
forcing SCAN_GATE off so that STOP_L1 will work in scan mode.

      This feedback path is already part of most latches in the CMOS
methodology.  Some have it built into the book and some have it in
the functional logic.