Browse Prior Art Database

Method of Reducing Dram Power Dissipation With Segmented Bitlines

IP.com Disclosure Number: IPCOM000100175D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new power-saving concept using segmented bitlines. Bitlines are segmented with pass gates. Only those bitline segments between the sense amplifier and the selected segment (inclusive) are moved when the sense amplifier is latched. This decreases power and di/dt noise during normal access and refresh cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Method of Reducing Dram Power Dissipation With Segmented Bitlines

       Disclosed is a new power-saving concept using segmented
bitlines.  Bitlines are segmented with pass gates. Only those bitline
segments between the sense amplifier and the selected segment
(inclusive) are moved when the sense amplifier is latched. This
decreases power and di/dt noise during normal access and refresh
cycles.

      The new scheme is schematically shown in the figure. The
bitlines are segmented into four segments with NMOS pass transistors.
The number of segments can be changed to suit a particular design.
Also CMOS pass gates can be used to avoid boosting the gates of NMOS
pass transistors.  When a wordline is chosen, only those bitline
segments between the selected segment and the sense amplifier are
moved by the sense amplifier. For example, if WL0 is chosen, only
bitline segment 0 is moved by the SA. If WL2 is chosen, bitline
segments 0, 1, and 2 are moved by the SA. Employing this method saves
power except for the wordlines in bitline segment 3.

      Array power saved during a refresh period can be estimated as
follows. Assume that a bitline is segmented into N equal segments
with M wordlines per segment. Power dissipation of the conventional
scheme, Pcon would be:
Pcon V CBL $ N $ M
 where CBL = bitline capacitance.
 With the new scheme, power dissipation Pnew would be:
      Pnew V M $ CBL $ (1 + 2 + ... + N) = M
$ CBL $ N + 1 .               ...