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Optimized Reference Level Generator for Two-Step Flash ADC

IP.com Disclosure Number: IPCOM000100179D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Hauviller, P: AUTHOR

Abstract

The generator described herein comprises two sample- and-hold circuits referenced (SH) SH1 and SH2, a three-bit flash ADC (analog-to-digital converter) a three-bit DAC (digital-to-analog converter) and a voltage reference circuit. This implementation allows building a six-bit two-step ADC and a 20-MHz operating frequency can be easily achieved using an advanced analog - BICMOS.

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Optimized Reference Level Generator for Two-Step Flash ADC

       The generator described herein comprises two sample-
and-hold circuits referenced (SH) SH1 and SH2, a three-bit flash ADC
(analog-to-digital converter) a three-bit DAC (digital-to-analog
converter) and a voltage reference circuit. This implementation
allows building  a six-bit two-step ADC and a 20-MHz operating
frequency can be easily achieved using an advanced analog - BICMOS.

      The block schematic of the ADC circuit is shown in Fig. 1. Note
that the SH circuit settling time is masked since we use two SHs; the
second SH get the next sample when the ADC is converting the current
sample from the first SH. The SH circuits have to operate within 50
nS.

      The complete schematic of the reference level generator is
shown in Fig. 2. The circuit operates in two phases (1, 2) driven by
two overlaping clocks (CK1, CK2).

      PHASE 1 (Determination of MSBs): During phase 1, the circuit
generates to the three-bit ADC the eight reference levels for the
MSBs determination. Since the switches S0 and S1 are closed (suppose
S0 is perfect), the register 8R is shorted and an 8I current flows in
the resistor ladder. In that case, the reference levels are spaced by
8xRI (=160 mV) as shown in Fig. 3. The three-bit ADC converts the
analog input into B5, B4, and B3; then the DAC logic control circuit
inverts it and subtracts 001.

      PHASE 2 (Determination of LSBs): The rising edge of CK2
activa...